Metallization technology for very-large-scale integration circuits |
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Authors: | A.K. Sinha |
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Affiliation: | Bell Laboratories, Murray Hill, NJ 07974, U.S.A. |
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Abstract: | This review summarizes the results of a program whose goals were to develop (a) high conductivity refractory silicide gates, (b) electromigration-resistant fine-line aluminum interconnects, (c) small geometry electromigration-resistant contacts to shallow junctions and (d) two-level interconnect systems. There is a critical need for these innovations, since the chip area in very-large-scale integration circuits tends to be interconnect dominated. Also discussed are the effects of shrinking design rules on the RC time constants of various interconnect structures. |
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