A 100-MHz 64-tap FIR digital filter in 0.8-μm BiCMOS gate array |
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Authors: | Yoshino T. Jain R. Yang P.T. Davis H. Gass W. Shah A.H. |
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Affiliation: | Texas Instrum. Inc., Dallas, TX; |
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Abstract: | A 64-tap FIR (finite impulse response) digital filter that has been designed using a newly developed filter compiler and fabricated in a 0.8-μm triple-level interconnect BiCMOS gate array technology is presented. The filter has been tested and is fully functional at a 100-MHz clock rate. These results are obtained by combining an optimized architecture and gate array floorplan with submicrometer BiCMOS technology. The filter occupies 49 mm2, which is approximately two-thirds of the 100 K gate array core. The design uses an equivalent of 55 K gates (two-input NAND gates). The device input/output are 100 K emitter-coupled-logic (ECL) compatible |
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