一种低功耗高性能自举采样开关

提出了一种基于TSMC 40 nm/0.9 V CMOS工艺设计的适用于音频范围的低功耗高性能栅压自举采样开关电路。通过PMOS晶体管的衬底和漏极相连接代替了时钟放大模块，极大降低了电路整体的功耗。在输入端增加了一个NMOS晶体管，随着开关时钟的开启/关闭，通过抑制核心采样晶体管的体效应，可以有效提高开关线性度。鉴于音频信号的范围，选用频率为19.53 kHz、幅值为0.3 V的正弦波信号进行10 MHz采样频率的高速采样仿真，与传统结构相比，有效位数(ENOB)、信噪比(SNR)、无杂散动态范围(SFDR)和总谐波失真(THD)四项性能指标分别提升了5.5%、3.7%、13.8%和5.4%,并且功耗降低了36.8%。

A Low-Power and High-Performance Bootstrap Sampling Switch

A low-power, high-performance gate voltage bootstrap sampling switch circuit was designed in TSMC 40 nm/0.9 V CMOS process for the application of audio signal sampling. The average power consumption of the overall switch circuit was greatly reduced by a novel shorting-connection topology of bulk-drain of PMOS transistor instead of a clock amplifier module. An NMOS transistor was specifically added to the input terminal and turned on/off along with the switched clock, so the switching linearity could be effectively improved and benefited from the suppressing of the body effect of the core sampling transistor. A sine wave signal, which was 19.53 kHz frequency and 0.3 V amplitude as a simulated audio signal was input into the proposed switching circuit, and then a high-speed data sampling simulation with a 10 MHz sampling frequency was carried out. Compared with the traditional switch circuit structure, four dynamic performance indexes in terms of the effective number of bit (ENOB), signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR) and total harmonic distortion (THD) are improved by 5.5%, 3.7%, 13.8% and 5.4%, respectively. Meanwhile, the power consumption is reduced by 36.8%.