| 一种符合JESD204C协议的并行FEC译码器 |
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| 引用本文： | 赵文飞,王永禄,陈刚. 一种符合JESD204C协议的并行FEC译码器[J]. 微电子学, 2023, 53(1): 50-54 |
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| 作者姓名： | 赵文飞 王永禄 陈刚 |
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| 作者单位： | 重庆邮电大学, 重庆 400065;模拟集成电路国家级重点实验室, 重庆 400060;模拟集成电路国家级重点实验室, 重庆 400060;中国电子科技集团公司 第二十四研究所, 重庆 400060 |
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| 基金项目： | 模拟集成电路国家级重点实验室基金资助项目(6142802200101) |
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| 摘 要： | 基于JESD204C协议，设计了一种适用于64B/66B链路层的并行FEC译码器。该电路采用64位并行处理方案，降低了电路对时钟频率的要求。针对协议使用的缩短(2074,2048)二进制循环码，设计了快速旋转电路，降低了电路设计的复杂度。使用Modelsim软件完成了功能验证，结果表明，译码器能够完成数据收发、纠错和报错等功能。采用了TSMC 65 nm标准数字工艺库，在Design Compiler平台上完成了逻辑综合，报告显示，译码器电路工作频率为500 MHz时，时间裕度为0.10 ns,单通道数据处理速度可达32 Gbit/s。
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| 关 键 词： | JESD204C 并行设计 FEC译码器 缩短循环码 64B/66B链路层 |
| 收稿时间： | 2022-01-18 |
A Parallel FEC Decoder for JESD204C Protocol |
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| ZHAO Wenfei,WANG Yonglu,CHEN Gang. A Parallel FEC Decoder for JESD204C Protocol[J]. Microelectronics, 2023, 53(1): 50-54 |
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| Authors: | ZHAO Wenfei WANG Yonglu CHEN Gang |
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| Affiliation: | Chongqing University of Posts And Telecommunications, Chongqing 400065, P.R.China;National Laboratory of Science and Technology on Analog Integrated Circuit, Chongqing 400060, P.R.China;National Laboratory of Science and Technology on Analog Integrated Circuit, Chongqing 400060, P.R.China;The 24th Research Institute of China Electronics Technology Corporation, Chongqing 400060, P.R.China |
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| Abstract: | Based on JESD204C protocol, a parallel FEC decoder for 64B/66B link layer was designed. 64 bit parallel scheme was adopted in it, which reduced the requirement of clock frequency. For the shortened (2074,2048) binary cyclic code in the protocol, a fast rotation circuit was designed. This circuit could be used to reduce the complexity of design. According to the functional verification test of Modelsim, the results show that the decoder can send and receive the data, and correct and report the error. On the Design Compiler platform, TSMC 65 nm standard digital process library is used for logic synthesis. The report shows that when the working frequency of the decoder circuit is 500 MHz, the slack time is 0.10 ns, and the speed of single channel data processing can reach 32 Gbit/s. |
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| Keywords: | JESD204C parallel design FEC decoder shortened cyclic code 64B/66B link layer |
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