动态自适应低密度奇偶校验码译码器的FPGA实现

在复杂深空通信环境中，自适应能力的强弱对低密度奇偶校验(LDPC)码译码器能否保持长期稳定工作具有重要影响。该文通过对DVB-S2标准LDPC码译码器各功能模块的IP化设计，将动态自适应理论参数化映射到各功能模块中，实现动态自适应LDPC码译码器的设计。基于Stratix IV系列FPGA的验证结果表明，动态自适应LDPC译码器可以满足不同码率码长及不同性能需求下的译码。同时，单译码通道可以保证译码数据信息吞吐率达到40.9~71.7 Mbps。

Design of Dynamic Adaptive LDPC Decoder Based on FPGA

Faced with the complex environment of deep space communication, the adaptive capacity can have an impact on the ability of the Low Density Parity Check (LDPC) code decoder to maintain long-term stability. This paper proposes a design method of dynamic adaptive LDPC code decoder. Through the IP-based design of each function module, the design method of dynamic adaptive can be mapped to each function module in DVB-S2 LDPC code decoder. The verification results based on the Stratix IV FPGA show the dynamic adaptive LDPC code decoder not only can decode under the different code length and code rate, but also can decode under the different decoding performance. Meanwhile, the single-channel decoder can ensure the information throughput to reach to 40.9~71.7 Mbps.