Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors |
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| Authors: | Yiming Li Jam-Wem Lee Hung-Mu Chou |
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| Affiliation: | (1) Department of Computational Nanoelectronics, Nano Device Laboratories, Hsinchu, 300, Taiwan;(2) Microelectronics and Information Systems Research Center, National Chiao Tung University, Hsinchu, 300, Taiwan;(3) Department of Electrophysics, National Chiao Tung University, Hsinchu, 300, Taiwan |
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| Abstract: | In this paper we numerically examine the electrical characteristics of surrounding-gate strained silicon nanowire field effect transistors (FETs) by changing the radius (RSiGe) of silicon-germanium (SiGe) wire. Due to the higher electron mobility, the n-type FETs with strained silicon channel films do enhance driving capability (∼8% increment on the drain current) in comparison with the pure Si one. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), and the gate capacitance (CG) are estimated with respect to different gate length (LG), gate bias (VG), and RSiGe. For short channel effects, such as Vt roll-off and DIBL, the surrounding-gate strained silicon nanowire FET sustains similar characteristics with the pure Si one. |
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| Keywords: | strained silicon nanowire FET surrounding-gate drain induced barrier height lowering threshold-voltage roll-off gate capacitance simulation |
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