| 串行数字锁相频率合成器的设计 |
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| 引用本文： | 李希密. 串行数字锁相频率合成器的设计[J]. 舰船电子对抗, 2005, 28(5): 61-64 |
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| 作者姓名： | 李希密 |
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| 作者单位： | 船舶重工集团公司723所,扬州225001 |
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| 摘 要： | 介绍了一种利用AT89S52单片机控制数字锁相环LMX2316的低相位噪声频率合成器，分析了环路的带内相位噪声以及环路的锁定时间与环路带宽的关系，讨论了环路滤波器的设计，最后得到了与分析相符合的结果。
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| 关 键 词： | 数字锁相环 单片机 频率合成器 |
| 文章编号： | CN32-1413(2005)05-0061-04 |
| 收稿时间： | 2005-01-25 |
| 修稿时间： | 2005-01-25 |
Design of Serial Digital Phase-locked Frequency Synthesizer |
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| LI Xi-mi. Design of Serial Digital Phase-locked Frequency Synthesizer[J]. Shipboard Electronic Countermeasure, 2005, 28(5): 61-64 |
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| Authors: | LI Xi-mi |
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| Affiliation: | The 723 Institute of CSIC, Yangzhou 225001, China |
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| Abstract: | This paper introduces a kind of low phase noise frequency synthesizer which uses AT89S52 single chip processor to control digital phase-locked loop LMX2316, analyses the in-band phase noise and the relations between lock time and loop bandwidth of loop, discusses the design of the loop filter, finally obtains the results according with the analysis. |
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| Keywords: | digital phase-locked loop single chip processor frequency synthesizer |
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