Si Wafer Thinning Techniques Compatible With Epitaxy of CdTe Buffer Layers |
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Authors: | J K Markunas R N Jacobs P J Smith J Pellegrino |
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Affiliation: | 1.U.S. Army RDECOM CERDEC Night Vision and Electronic Sensors Directorate,Ft. Belvoir,USA |
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Abstract: | Reduction of threading dislocation density is critical for improving the performance of HgCdTe detectors on lattice-mismatched
alternative substrates such as Si. CdTe buffer layers grown by molecular beam epitaxy (MBE), with thicknesses on the order
of 8 μm to 12 μm, have helped reduce dislocation densities in HgCdTe layers. In this study, the reduction of threading dislocation densities
in CdTe buffer layers grown on locally thinned Si substrates was examined. A novel Si back-thinning technique was developed
that maintained an epiready front surface and achieved Si thicknesses as low as 1.9 μm. Threading dislocation densities, acquired by defect decoration techniques, were reduced by as much as 60% for CdTe buffer
layers grown on these thinned regions when compared with unthinned regions. However, this reduction is inconsistent with prior
notions that threading dislocation propagation is dominated by image forces. Instead, the thickness gradient of thinned Si
may play a larger role. |
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