| 一种新型2-DCT/IDCT结构的设计与实现 |
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| 引用本文： | 傅宇卓,王嘉芳,胡铭曾. 一种新型2-DCT/IDCT结构的设计与实现[J]. 电子学报, 2002, 30(Z1): 2126-2129 |
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| 作者姓名： | 傅宇卓 王嘉芳 胡铭曾 |
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| 作者单位： | 1. 上海交通大学计算机系, 上海, 200030;2. 黑龙江大学计算机系, 黑龙江哈尔滨, 150080;3. 哈尔滨工业大学320信箱, 黑龙江哈尔滨, 150001 |
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| 基金项目： | 国家高技术研究发展计划(863计划)，863-306-03-07-2， |
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| 摘 要： | 本文根据MPEG-2视频编码的特点,设计了仅由一个1-DCT核完成的2-DCT/IDCT结构,该结构的转换矩阵通过SRAM实现,具备双端口的输入输出,数据吞吐率较高,能够有效节省芯片面积.1-DCT核由7个乘法器组成,乘法器可以根据计算速度的快慢灵活设计.为了解决双端口无冲突的存储访问,提出了一个数据排列方案.由于乘法器的乘数之一为常数,我们设计了一种常数修改方案能够有效的降低成法器的硬件开销.该2-DCT/IDCT结构通过了FPGA验证,具有较强的工程实用价值.
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| 关 键 词： | 2-DCT/IDCT 乘法器 FPGA验证 |
| 文章编号： | 0372-2112(2002)12A-2126-04 |
| 收稿时间： | 2002-06-10 |
| 修稿时间： | 2002-06-10 |
The Design and Implementation of a Novel 2-DCT/IDCT Architecture |
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| FU Yu-zhuo,WANG Jia-fang,HU Ming-zeng. The Design and Implementation of a Novel 2-DCT/IDCT Architecture[J]. Acta Electronica Sinica, 2002, 30(Z1): 2126-2129 |
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| Authors: | FU Yu-zhuo WANG Jia-fang HU Ming-zeng |
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| Affiliation: | 1. Computer Department, Shanghai Jiaotong University, Shanghai 200030, China;2. Computer Department, Heilongjiang University, Harbin, Heilongjiang 150080, China;3. P.O. BOX 320, Harbin Institute of Technology, Harbin, Heilongjiang 150001, China |
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| Abstract: | The paper gives a 2-DCT/IDCT architecture implemented by 1-DCT core according to the characteristic of MPEC-2 video encoder.The architecture's transform matrix is implemented by SRAM which has dual ports for input/output. It has the advantage of high data throughput rate and low chip area. The 1-DCT core is compared with seven multipliers which could be designed according to the computing speed.The paper gives a data arrangement scheme in order to avoid storage confusion of dual ports. What's more, a novel multiplier architecture is given by modifying constant precision which can reduce the hardware cost efficiently. The architecture is validated by FPGA which proves its engineering value. |
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| Keywords: | 2-DCT/IDCT |
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