可演化组合逻辑数字电路的静电放电抗扰特性

为研究可演化组合逻辑电路对静电放电的抗扰特性,提出了一种基于Cartesian模型和虚拟重配置技术的可演化组合电路系统模型,按照静电放电抗扰度测试标准IEC 61000-4-2分析了电路逻辑功能的受扰规律,归纳为单极性逻辑翻转和瞬态逻辑击穿2种故障模型。利用故障注入的方法模拟静电放电干扰环境,在故障节点比例逐渐增加的条件下进行了功能电路的演化设计试验。结果表明：当静电干扰事件较少时,演化电路可以快速稳定的演化生成功能完备的数字电路;当静电干扰事件频发且造成大量逻辑单元受扰时,其仍能演化生成适应度达0.9的功能电路。因此,可演化组合逻辑电路在逐渐恶劣的静电放电干扰环境下表现出高可靠的抗扰特性。

Anti-electrostatic Discharge Interference Characteristics of Evolvable Combinational Circuits

In order to investigate the anti-electrostatic discharge(ESD) interference characteristics of evolvable combinational circuits,we proposed a general evolvable model of digital circuits combining virtual reconfigurable circuits’ technology with the Cartesian genetic programming ideas.ESD electromagnetic pulse effect experiments were carried out based on IEC 61000-4-2.Thereby,the mechanisms of different interference patterns were analyzed and divided into two types,single polar upsets and transient logical breakdown.Evolution experiments were also carried out when increasing the number of faults,in which the ESD interference environment was simulated by using fault-injection method.The experimental results show that the evolvable digital circuits are immune to low-level fault nodes percentage range.And the circuit can still maintain a fitness of approximately 0.9 even with higher fault node percentages under frequent ESD interferences.It is concluded that the anti-interference ability of evolvable digital circuits is highly reliable.