X-tolerant Test Data Compaction with Accelerated Shift Registers |
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Authors: | Martin Hilscher Michael Braun Michael Richter Andreas Leininger Michael Gössel |
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Affiliation: | 1. Institut für Informatik, Universit?t Potsdam, August-Bebel-Strasse 89, 14482, Potsdam, Germany 2. Verigy Germany GmbH, Herrenberger Strasse 130, 71034, B?blingen, Germany 3. Infineon Technologies AG, Am Campeon 1–12, 85579, Neubiberg, Germany
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Abstract: | Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution. |
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