基于FPGA的乘法器实现结构分析与仿真

现场可编程门阵列(FPGA)的快速发展为数字信号处理(DSP)系统设计提供了一种新的解决方案，而乘法运算是DSP领域内的一种基本运算，应用极为广泛，对乘法运算基于FPGA的实现结构进行研究具有重要意义。本文分析乘法运算的特点，给出了几种适应FPGA实现的乘法器结构。并在Xilinx公司的ISE 4．1i软件环境下，采用VHDL和VIRELOG硬件描述语言进行了设计实现并对其性能进行了比较分析。

The Analysis and Simulating for FPGA-Based Multiplier Implementation Structures

The progress in field programmable gate arrays (FPGAs) provides new options for DSP design engineers. And the multiplication is one of the most important operations in the field of digital signal processing (DSP). Hence, in this paper,the characteristic of multiplication is analyzed and some different types of multiplier structures are offered. And the performance evaluation and comparison (area and speed) for these multiplier implementation structures have been carried out by utilizing the Hard Describe Language (VHDL and VIRELOG) and ISE software package V4.1i from Xilinx.