一种低成本128位高精度浮点SIMD乘加单元的设计与实现

SIMD单元集成已经成为提高处理器性能的重要途径之一。虽然定点SIMD单元的硬件复用低成本设计技术已经较为成熟,但是,大部分浮点SIMD单元的硬件设计还停留在简单的硬件复制方法上。本文针对日益增长的128位高精度浮点操作的计算需求,提出了其相应的SIMD低成本硬件结构方案。综合实验结果表明,所提出的SIMD浮点乘加单元比传统128位高精度浮点乘加单元具有更加优化的性能与面积参数。

Design and Implementation of a Low-Cost 128-bit Quadruple-Precision Floating-Point SIMD Fused Multiply-Add Unit

Incorporating the SIMD unit has become one of the important ways to improve the performance of processors.The reused low-cost hardware design method for the fixed-point SIMD unit is mature , but it is not the case for the floating-point SIMD unit , which still remains the simple replication design method.To address the increasing computation demand for 128-bit quadruple-precision floating- point operations , this paper proposes the hardware design of the low-cost 128-bit quadruple-precision floatingpoint SIMD fused multiply-add ( FMA ) unit.The experimental results show that the structure of the proposed FMA unit can be more optimized in performance and cost parameters in comparison to the traditional 128-bit quadruple-precision floating-point SIMD multiple-add unit.