| (2,1,7)维特比译码器的并行算法实现 |
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| 引用本文： | 强秀丽,刘党辉,秦桂枝. (2,1,7)维特比译码器的并行算法实现[J]. 装备指挥技术学院学报, 2000, 11(6): 82-86 |
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| 作者姓名： | 强秀丽 刘党辉 秦桂枝 |
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| 作者单位： | 装备指挥技术学院试验工程系 |
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| 摘 要： | 在卫星通信中，高、中速卷积码的应用极为广泛，译码器的硬件实现一直受速度的制约，随着微电子技术的发展，可编程器件的广泛使用，对于中高速(2，1，7)卷积编码的Viterbi(维特比)译码器，完全由硬件实现已成为可能。在并行算法设计中，ACS运算器的硬件规模占了整个译码器硬件的一半以上，如果在FPGA(可编程门阵列)中使用多路复用技术来实现(2，1，7)Viterbi译码，可以减少约2／3的器件规模。
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| 关 键 词： | 维特比译码器 卷积编码 硬件实现 Viterbi译码 卷积码 卫星通信 多路复用技术 并行算法 运算器 可编程器件 |
| 修稿时间： | : |
(2, 1, 7) Viterbi Decoder Parallel Algorithm Implementation |
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| Qiang Xiuli Liu Danghui Qin Guizhi. (2, 1, 7) Viterbi Decoder Parallel Algorithm Implementation[J]. Journal of the Academy of Equipment Command & Technology, 2000, 11(6): 82-86 |
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| Authors: | Qiang Xiuli Liu Danghui Qin Guizhi |
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| Affiliation: | Department of Test Engineering.Institute of Command and Technology of Equipment |
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| Abstract: | The application of middle/high speed convolutional codes is very common in communication , but the speed of decoder is limited by hardware performance. With the development of microelectronics and programmable logic array device, the (2, 1, 7) Viterbi decoder hardware implementation is possible. In parallel algorithms the ACS cells occupy more than half of the whole decoder. To cut off the scale we use multiple reusing technologies on FPGA, which can save the size by 2/3. |
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| Keywords: | FPGA convolutional codes generator polynomials Viterbi decode algorithm multiple using technology |
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