| 一种改进式数字频率合成器的设计与仿真 |
| |
| 引用本文： | 石强.一种改进式数字频率合成器的设计与仿真[J].系统仿真技术,2009,5(2):122-124,134. |
| |
| 作者姓名： | 石强 |
| |
| 作者单位： | 上海大学,通信与信息工程学院,上海,200072 |
| |
| 摘 要： | 为了获得良好的频率合成与跟踪效果，依据锁相环的基本工作原理，采用锁相嵌套结构设计了1种改进式数字频率合成器。理论分析和仿真结果表明，这种设计方法能有效地实现频率合成，并且具有较强的抗噪性能和较低的环路功耗。
|
| 关 键 词： | 频率合成 锁相环 功率谱 相位噪声 |
Design and Simulation of an Improved Digital Frequency Synthesizer |
| |
| SHI Qiang.Design and Simulation of an Improved Digital Frequency Synthesizer[J].System Simulation Technology,2009,5(2):122-124,134. |
| |
| Authors: | SHI Qiang |
| |
| Affiliation: | SHI Qiang( School of Communication and Information Engineering, Shanghai University, Shanghai 200072, China) |
| |
| Abstract: | In order to achieve frequency synthesize and tracking, an improved digital phase-locked frequency synthesizer is designed using phase-locked nested structure based on the principle of phase- locked loop （PLL） in this paper. Theory analysis and simulation results show that the proposed design method can achieve frequency synthesize effectively with better anti-noise performance and lower power dissipation. |
| |
| Keywords: | frequency synthesize phase-locked loop （PLL） power spectrum phase noise |
| 本文献已被 维普 万方数据 等数据库收录！ |
|
