首页 | 本学科首页   官方微博 | 高级检索  
     


Runtime home mapping for effective memory resource usage
Authors:Mario Lodde,José   FlichAuthor Vitae
Affiliation:Departamento DISCA Universitat Politècnica de València, Camino de Vera, S/N 46022 Valencia, Spain
Abstract:In tiled Chip Multiprocessors (CMPs) last-level cache (LLC) banks are usually shared but distributed among the tiles. A static mapping of cache blocks to the LLC banks leads to poor efficiency since a block may be mapped away from the tiles actually accessing it. Dynamic policies either rely on the static mapping of blocks to a set of banks (D-NUCA) or rely on the OS to dynamically load pages to statically mapped addresses (first-touch).
Keywords:Chip multiprocessors   Network-on-chip   Cache hierarchy   Coherence protocols
本文献已被 ScienceDirect 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号