A survey of memory architecture for 3D chip multi-processors |
| |
Authors: | Yuang Zhang Li Li Zhonghai Lu Axel Jantsch Minglun Gao Hongbing Pan Feng Han |
| |
Affiliation: | 1. Institute of VLSI Design, Key Laboratory of Advanced Photonic and Electronic Materials, Nanjing University, Nanjing, China;2. Department of Electronic, Computer and Software Systems, School of Information and Communication Technology, KTH – Royal Institute of Technology, Stockholm, Sweden |
| |
Abstract: | 3D chip multi-processors (3D CMPs) combine the advantages of 3D integration and the parallelism of CMPs, which are emerging as active research topics in VLSI and multi-core computer architecture communities. One significant potentiality of 3D CMPs is to exploit the diversity of integration processes and high volume of vertical TSV bandwidth to mitigate the well-known “Memory Wall” problem. Meanwhile, the 3D integration techniques are under the severe thermal, manufacture yield and cost constraints. Research on 3D stacking memory hierarchy explores the high performance and power/thermal efficient memory architectures for 3D CMPs. The micro-architectures of memories can be designed in the 3D integrated circuit context and integrated into 3D CMPs. This paper surveys the design of memory architectures for 3D CMPs. We summarize current research into two categories: stacking cache-only architectures and stacking main memory architectures for 3D CMPs. The representative works are reviewed and the remaining opportunities and challenges are discussed to guide the future research in this emerging area. |
| |
Keywords: | 3D integrated circuit Chip multi-processor Memory architecture Non-uniform cache architecture |
本文献已被 ScienceDirect 等数据库收录! |
|