Bias polarity dependent effects of P+floating gate EEPROMs |
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| Authors: | Kuo C Tsu-Jae King Chenming Hu |
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| Affiliation: | Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA; |
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| Abstract: | EEPROM devices with either N-type or P-type floating gate were fabricated and characterized. Program/erase speeds and stress-induced leakage current-related retention characteristics for both types of devices are explained. Discrepancies between previously published reports on P-type floating gate devices and PMOS gate current measurements are resolved. The feasibility of integrating P-type floating gate EEPROMs in high density memory arrays is examined. |
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