多核混合可重构计算系统MRCS的设计

设计了一种面向计算密集型应用的多核混合架构可重构计算系统MRCS。其可重构处理器中的可重构阵列计算单元负责密集规则的运算,浮点处理器负责离散运算,配合灵活的本地缓冲,有效地提高了多核可重构计算系统对算法的适应性。实现了一个能够稳定地运行在100 MHz的基于FPGA的MRCS原型,并通过分别映射大维度浮点矩阵乘法、IDCT算法和运动估计算法进行性能验证。实验结果表明MRCS具有更高的计算效率和灵活性。

Design of hybrid architecture of multi core reconfigurable computing system MRCS

Hybrid architecture of multi core reconfigurable computing system, named MRCS, is designed for compute intensive oriented application. In MRCS, reconfigurable array computing units perform the task of dense and regular operations; floating point units are responsible for the discrete computing operations. In addition, with flexible local buffers, this architecture could effectively improve the adaptability of reconfigurable computing system to application. An FPGA based MRCS prototype which could operate steadily at 100 MHz has been implemented. With mapping of the large dimensional floating point matrix multiplication, IDCT algorithm and motion estimation algorithm, the computing performances are validated. The experimental results show that MRCS has higher computing efficiency and flexibility.