| Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA |
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| 引用本文： | Gao,Haixi,Yang,Yintang,an,Dong,Gang. Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA[J]. 半导体学报, 2005, 26(5): 893-898 |
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| 作者姓名： | Gao Haixi Yang Yintang an Dong Gang |
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| 作者单位： | 西安电子科技大学微电子研究所 西安710071(高海霞，杨银堂)，西安电子科技大学微电子研究所 西安710071(董刚) |
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| 摘 要： | Based on architecture analysis of island style FPGA,area and delay models of LUT FPGA are proposed.The models are used to analyze the effect of LUT size on FPGA area and performance.Results show optimal LUT size obtained by computation models is the same as that from experiments:a LUT size of 4 produces the best area results,and a LUT size of 5 provides the better performance.
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| 关 键 词： | FPGA；LUT；computation models；area；delay |
Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA |
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| Gao Haixia,Yang Yintang,Dong Gang. Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA[J]. Chinese Journal of Semiconductors, 2005, 26(5): 893-898 |
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| Authors: | Gao Haixia Yang Yintang Dong Gang |
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| Abstract: | Based on architecture analysis of island-style F PGA,area and delay models of LUT FPGA are proposed.The models are used to analyze the effect of LUT size on FPGA area and performance.Results show optimal LUT size obtained by computation models is the same as that from experiments:a LUT size of 4 produces the best area results,and a LUT size of 5 provides the better performance. |
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| Keywords: | FPGA LUT computation models area delay |
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