Evaluating the energy consumption and the silicon area of on-chip interconnect architectures

Sophisticated on-chip interconnects using packet and circuit switching techniques were recently proposed as a solution to non-scalable shared-bus schemes currently used in Systems-on-Chip (SoCs) implementation. Different interconnect architectures have been studied and adapted for SoCs to achieve high throughput, low latency and energy consumption, and efficient silicon area. Recently, a new on-chip interconnect architecture by adapting the WK-recursive network topology structure has been introduced for SoCs. This paper analyses and compares the energy consumption and the area requirements of Wk-recursive network with five common on-chip interconnects, 2D Mesh, Ring, Spidergon, Fat-Tree and Butterfly Fat-Tree. We investigated the effects of load and traffic models and the obtained results show that the traffic models and load that ends processing elements has a direct effect on the energy consumption and area requirements. In these results, WK-recursive interconnect generally has a higher energy consumption and silicon area requirements in heavy traffic load.