| CCSDS中位平面编码的FPGA优化实现 |
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| 引用本文： | 毛峡,湛杰.CCSDS中位平面编码的FPGA优化实现[J].电视技术,2011,35(7):52-55. |
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| 作者姓名： | 毛峡 湛杰 |
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| 作者单位： | 北京航空航天大学电子信息工程学院; |
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| 摘 要： | CCSDS图像压缩算法是空间数据系统咨询委员会针对深空探测图像制定的图像压缩标准.该算法的码率可控、复杂度较低,而且算法结构适合于硬件实现,支持对空间数据的高速实时处理.给出了基于可编程逻辑电路硬件的位平面编码算法的设计与实现方法,并通过分析直流、交流系数编码过程中各模块内部和模块间的关系,设计了流水线,使系统处理速度...
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| 关 键 词： | CCSDS 位平面编码 FPGA 流水线设计 图像压缩 Verilog HDL |
Implementation of Bit Plane Encoder in CCSDS Based on FPGA |
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| MAO Xia,ZHAN Jie.Implementation of Bit Plane Encoder in CCSDS Based on FPGA[J].Tv Engineering,2011,35(7):52-55. |
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| Authors: | MAO Xia ZHAN Jie |
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| Affiliation: | MAO Xia,ZHAN Jie (School of Electronic and Information Engineering,Beihang University,Beijing 100191,China) |
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| Abstract: | CCSDS image data compression standard is established by Consultative Committee for Space Data Systems (CCSDS) and applies to data compression applications of space missions. The algorithm has low complexity, and makes the coded data rate to be controlled, meanwhile the configuration of the algorithm is suitable for hardware implementation, and the algorithm provides real-time processing with space image data. The FPGA-based implementation of Bit Plane Encoder (BPE) is presented, and through the use of the p... |
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| Keywords: | CCSDS BPE FPGA pipeline design image data compression Verilog HDL |
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