| UPS并机数字锁相误差分析 |
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| 引用本文： | 周朝阳,于玮,徐德鸿. UPS并机数字锁相误差分析[J]. 电源技术应用, 2006, 9(11): 32-36 |
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| 作者姓名： | 周朝阳 于玮 徐德鸿 |
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| 作者单位： | 浙江大学电气工程学院，浙江大学电气工程学院，浙江大学电气工程学院 浙江 杭州 310027，浙江 杭州 310027，浙江 杭州 310027 |
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| 摘 要： | 针对不间断电源(UPS)并联系统同步问题,进行锁相误差分析,并探讨了减少锁相误差的措施和方案。通过在两台30kVA样机上进行并联实验,验证了方案的正确性。
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| 关 键 词： | 同步 锁相 并联 UPS |
| 收稿时间： | 2006-04-20 |
Analysis of Phase Lock Error for Parallel UPS |
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| ZHOU Chao-yang, YU Wei, XU De-hong. Analysis of Phase Lock Error for Parallel UPS[J]. Power Supply Technologles and Applications, 2006, 9(11): 32-36 |
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| Authors: | ZHOU Chao-yang YU Wei XU De-hong |
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| Affiliation: | College of Electrical Engineering, Zhejiang University, Hangzhou Zhejiang 310027, China |
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| Abstract: | In order to achieve synchronized output voltage of parallel working UPS, the phase lock error analysis of parallel UPS and methods to reduce phase lock error are proposed. The experimental results obtained from two 30kVA parallel working UPS are presented to prove the feasibility and features of the proposed scheme. |
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| Keywords: | synchronization: phase locked loop parallel system UPS |
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