Impact of gate-leakage currents on CMOS circuit performance

Ultra-thin gate dielectrics are exploited in fabrication of MOSFETs featuring channel lengths in the decananometer range: according to the ITRS oxide thickness in the order of 1 nm will be used in 2005 for ultra-short channel CMOS. For such aggressively scaled devices, gate-leakage currents represent a critical issue. In this paper, a study on the impact of direct-tunneling (DT) current on the performance of a wide variety of CMOS circuits is presented. The approach relies on a mixed-mode simulation approach, which allows for predicting the correlation of major performance indices with oxide thickness.