A current-steering self-calibration 14-bit 100-MSPs DAC |
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Authors: | Qiu Dong Fang Sheng Li Ran Xie Renzhong Yi Ting Hong Zhiliang |
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Affiliation: | State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203,China |
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Abstract: | This paper presents the design and implementation of a 14-bit,100 MS/s CMOS digital-to-analog converter(DAC).Analog background self-calibration based on the concept of analog current trimming is introduced.A constant clock load switch driver,a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance.The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33× 0.97 mm2 of the core area.The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog,respectively.The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB,respectively.The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency. |
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Keywords: | DAC high speed high resolution self-calibration calibration period randomization |
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