一种新型的高速时钟数据恢复电路的设计和验证

针对高速(Gbit/s)串行数据通信应用,提出了一种混合结构的高速时钟数据恢复电路。该电路结构结合鉴频器和半速率二进制鉴相器,实现了频率锁定环路和相位恢复环路的同时工作。和传统的双环路结构相比,在功耗和面积可比拟的前提下,该结构系统的复杂度低、响应速度快。电路采用1.8 V,0.18μm CMOS工艺流片验证,测试结果显示在2 Gbit/s伪随机数序列输入情况下,电路能正确恢复出时钟和数据。芯片面积约0.5 mm~2,时钟数据恢复部分功耗为53.6 mW,输出驱动电路功耗约64.5 mW,恢复出的时钟抖动峰峰值为45 ps,均方根抖动为9.636 ps。

Design and Validation of a New High Speed Clock and Data Recovery Circuit

A new high speed hybrid clock and data recovery circuit is presented that is suit- able for the application in Giga bit/s serial data communication.By adopting a frequency detector in parallel with a half-rate bang-bang phase detector,it achieves a cooperation of the frequency locked loop and the phase locked loop,compared to the traditional dual loop architecture,the new hybrid circuit shows faster response speed,smaller area,lower power dissipation and less complexity.Implemented in an 1.8 V 0.18μm 1P6M standard CMOS process,the test results show that,with a 2 Gbit/s PRBS input,the system can recover the data and clock correctly,the total area is 0.5 mm~2,the core power dissipation is 53.6 mW,the output buffer consumes 64.5 mW;the recovered clock has a 7.46 ps and 45 ps RMS jitter and peak-peak jitter respectively.