| 基于JTAG的SoC芯片调试系统设计 |
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| 引用本文： | 虞致国,魏敬和. 基于JTAG的SoC芯片调试系统设计[J]. 电子与封装, 2007, 7(7): 24-27,48 |
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| 作者姓名： | 虞致国 魏敬和 |
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| 作者单位： | 中国电子科技集团公司第58研究所,江苏,无锡,214035;中国电子科技集团公司第58研究所,江苏,无锡,214035 |
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| 摘 要： | 文章提出了一种基于IEEE 1149.1 JTAG协议的SoC调试接口,该设计支持寄存器查看和设置、CPU调试、IP核调试、边界扫描测试等功能。对该接口的整体结构框图到设计都进行了详细的阐述。该接口成功地应用于测控SoC中,具有很好的参考价值。
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| 关 键 词： | 系统芯片 JTAG 调试接口 扫描链 |
| 文章编号： | 1681-1070（2007）07-0024-04 |
| 修稿时间： | 2007-01-15 |
Design of SoC Debug System Based on JTAG |
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| YU Zhi-guo,WEI Jing-he. Design of SoC Debug System Based on JTAG[J]. Electronics & Packaging, 2007, 7(7): 24-27,48 |
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| Authors: | YU Zhi-guo WEI Jing-he |
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| Affiliation: | The 58^th Research Institute ofCETC, Wuxi 214035, China |
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| Abstract: | A debug system for SoC based on IEEE 1149.1 JTAG architecture is developed, which can give some powerful functions such as monitoring the registers, debugging and tracing the program flow of CPU, debugging IP core, profiling and scanning test, etc. The design is described from the overview to the detailed module design. This interface is successfully used in Intelligent Measurement and Control SoC. |
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| Keywords: | System-on-Chip JTAG debug interface scan test |
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