SET-based nano-circuit simulation and design method using HSPICE

This paper presents a simulation and design method for complementary SET-based nano-circuits from a practical circuit design point of view. HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth-Death Markov chain is demonstrated and verified with Coulomb characteristics. It shows reduced CPU time, improvement of accuracy, and more compatibility with other SPICE softwares on both Windows and Unix platforms. The proposed design methodology presents how to build static CMOS-like SET circuits, and demonstrates that conventional CMOS circuit design methodologies are all applicable to SET circuit designs based on the methodology. HSPICE simulation results show that, for 1 MΩ junction resistance, the power consumption of a SET NAND2 gate is less than 0.3 pW, and the propagation delay for a SET XOR2 gate is 29.8 ns while driving a 10 aF load.