Rapid Synthesis and Simulation of Computational Circuits in an MPPA |
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Authors: | David Grant Graeme Smecher Guy G F Lemieux Rosemary Francis |
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Affiliation: | (1) University of British Columbia, 2332 Main Mall, Vancouver, BC, Canada, V6T 1Z4;(2) University of Cambridge, 15 JJ Thomson Avenue, Cambridge, CB3 0FD, UK |
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Abstract: | A computational circuit is custom-designed hardware which promises to offer maximum speedup of computationally intensive software algorithms. However,
the practical needs to manage development cost and many low-level physical design details erodes much of the potential speedup
by distracting attention away from high-level architectural design. Instead, designers need an inexpensive, processor-like
platform where computational circuits can be rapidly synthesized and simulated. This enables rapid architectural evolution
and mitigates the risk of producing custom hardware. In this paper we present a tool flow (RVETool) for compiling computational
circuits into a massively parallel processor array (MPPA). We demonstrate the CAD runtime is on average 70× faster than FPGA
tools, with a circuit speed 5.8× slower than FPGA devices. Unlike the fixed logic capacity of FPGAs, RVETool can trade area
for simulation performance by targeting a wide range in the number of processor cores. We also demonstrate tool scalability
to very large circuits, synthesizing, placing, and routing a ≈1.6 million gate random circuit in 54 min. |
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