基于DLL的1.25G超宽带通信系统时钟生成电路

设计并实现了一个基于延时锁定环(DLL)、用于超宽带(UWB)无线通信系统的1.25GHz时钟生成电路。该时钟生成电路由两个DLL和一个自调谐LC滤波电路组成,输入125MHz的参考时钟,输出1.25GHz的差分时钟和间隔100ps的16相时钟。通过优化电荷泵电路有效地减小了静态相位误差,新式自调谐LC滤波电路的应用消除了工艺偏差对谐振的影响。在1.8V电源电压,SMIC0.18μmCMOS工艺下,该时钟生成电路在各种工作条件下均表现出良好的性能,在标准情况下静态相位误差仅为9ps,最大时钟抖动为10ps。当电感存在30%的工艺偏差时,滤波电路的谐振频率能够自动维持在1.25GHz上。

A DLL-based 1.25 G Clock Synthesizer for Impulse UWB System

This paper presents a delay-locked loop(DLL)-based 1.25 GHz CMOS clock synthesizer for impulse ultra-wideband(UWB) wireless communication system.Two DLLs and a self-tuning filter are applied in the synthesizer that outputs a 1.25 GHz high frequency clock and a 16-phase differential clock with 100 ps interval from a 125 MHz reference input.Improvement on the charge pump decreases the static phase error and novel self-tuning filter eliminates the deviation caused by process variation.The clock synthesizer gives good performance on different conditions of SMIC 0.18 μm CMOS process with 1.8 V power supply.The simulated static phase error is only 9ps and the peak-to-peak jitter is 10ps on the standard condition.The centre frequency of the filter is automatically tuned to 1.25 GHz in the presence of 30% inductor process variation.