基于Cache的HEVC运动补偿带宽优化设计

作为计算量最多的模块之一,运动补偿占用了解码器与片外数据存储器之间约70%的带宽,是实现超高清视频解码的瓶颈。通过所设计的基于Cache的HEVC运动补偿模块,在保证实时解码数据吞吐量的同时,有效减少了80%的带宽消耗。首先,利用由可复用滤波器构成的插值计算模块和2D Cache设计了可并行化流水线数据处理的运动补偿模块,满足计算过程中高数据吞吐量需求。其次,设计高效内部存储器RAM结构,并提出片内Cache功耗降低的有效解决方案。最后,利用了参考帧数据相关性,设计插值顺序重排,将Cache的硬件开销减少了87.5%。基于HM9.0的HEVC标准测试视频序列实验结构表明,该设计显著地减少了带宽消耗和硬件开销。

Design of Cache Based Bandwidth Reduction for HEVC Motion Compensation

Motion compensation is one of the most intensive computation components of video decoder, which is the bottleneck of super high vision real-time decoding by occupying around 70% bandwidth requirements. This paper proposes a cache based bandwidth reduction scheme for HEVC motion compensation, which can efficiently reduce more than 80% bandwidth consumption. Firstly, a parallelized pipeline motion compensation module is proposed, which consists of reconfigurable filter based on interpolation module and 2-D cache. This architecture ensures the huge throughput requirements of high resolution video decoding. Secondly, an internal memory organization is proposed to effectively reduce the power consumption of cache. Thirdly, this paper proposes an interpolation reordering scheme to efficiently use the locality of reference data. The reordering scheme contributes to reduce 87.5% hardware implementation cost of cache. The experiments are tested with HEVC standard testing video sequences under HM 9.0. The results indicate that our design can efficiently reduce the bandwidth and hardware cost.