| 基于FPGA的32位浮点加法器的设计 |
| |
| 引用本文： | 吉伟,黄巾,杨靓,黄士坦. 基于FPGA的32位浮点加法器的设计[J]. 微电子学与计算机, 2008, 25(6) |
| |
| 作者姓名： | 吉伟 黄巾 杨靓 黄士坦 |
| |
| 作者单位： | 西安微电子技术研究所,陕西,西安,710075 |
| |
| 摘 要： | 在综合分析各种浮点加法器算法的基础上,提出了一种符合TI格式标准的32位浮点加法器,同时兼顾了速度和面积两方面因素.本设计在virtex-4系列FPGA上进行了实现,最高速度可达到182.415MHz,资源占用也较为合理.
|
| 关 键 词： | 浮点加法器 TI 流水线 LOD |
Design of 32bit Floating-point Adder based on FPGA |
| |
| JI Wei,HUANG Jin,YANG Liang,HUANG Shi-tan. Design of 32bit Floating-point Adder based on FPGA[J]. Microelectronics & Computer, 2008, 25(6) |
| |
| Authors: | JI Wei HUANG Jin YANG Liang HUANG Shi-tan |
| |
| Abstract: | Put forward a design of 32bit floating-point adder according with TI format based on the analysis of all kinds of floating-point adders.This design satisfied with both speed and area factors and implemented on virtex-4 series FPGA, the highest running frequency is 182.415MHz and the area cost is rational compared to the entire resources. |
| |
| Keywords: | floating-point adder TI pipelining LOD |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
|
