Optimization of low-noise GaAs MESFET's

This paper presents a device design which is an effective way of reconciling the two conflicting requirements for low-noise GaAs MESFET's. Decreasing the effective value of gate length can be achieved, without penalty of increased gate metallization resistance, by the virtue of a proper gate-recess structure. This effect can be explained by the "effective gate length" concept. The pertinent fabrication techniques and the optimal noise-figure expression are given for an optimized structure with illustrated examples.