| 一种前端ASIC芯片测试系统的设计与实现 |
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| 引用本文： | 千奕,苏弘,孔洁,董成富,马晓莉,李小刚.一种前端ASIC芯片测试系统的设计与实现[J].核技术,2009,32(9). |
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| 作者姓名： | 千奕 苏弘 孔洁 董成富 马晓莉 李小刚 |
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| 作者单位： | 1. 中国科学院近代物理研究所,兰州,730000
2. 中国科学院近代物理研究所,兰州,730000;中国科学院研究生院,北京,100049 |
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| 基金项目： | 国家自然科学基金资助(10675153)项目 |
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| 摘 要： | 介绍了一种专用集成电路芯片性能测试系统的设计与实现,该芯片适用于构建硅探测器前端读出电子学.描述了测试系统主要硬件电路设计,基于CPLD的快读出控制时序发生模块的实现,利用并口线来模拟I2C总线的方法,系统的调试和主要性能的分析.
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| 关 键 词： | 测试系统 硬件设计 ASIC芯片 |
Design and implement of a test system for front-end ASIC chips |
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| QIAN Yi,SU Hong,KONG Jie,DONG Chengfu,MA Xiaoli,LI Xiaogang.Design and implement of a test system for front-end ASIC chips[J].Nuclear Techniques,2009,32(9). |
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| Authors: | QIAN Yi SU Hong KONG Jie DONG Chengfu MA Xiaoli LI Xiaogang |
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| Affiliation: | Institute of Modern Physics;Chinese Academy of Sciences;Lanzhou 730000;China;Graduate School;Beijing;100049;China |
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| Abstract: | A test system for front-end ASIC chip that developed for optimum performance with silicon strip detector was presented in this paper.The main circuit,implementation of a fast read-out control pulse generator based on CPLD and the realization of I2C bus using lines in parallel port were introduced.And the debugging and the performance analysis of the testing system were described. |
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| Keywords: | I2C CPLD |
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