32 nm CMOS工艺的单粒子多点翻转加固锁存器设计

随着集成电路工艺不断改进,电荷共享效应诱发的单粒子多点翻转已经成为影响芯片可靠性的重要因素.为此提出一种有效容忍单粒子多点翻转的加固锁存器:低功耗多点翻转加固锁存器(low power multiple node upset hardened latch,LPMNUHL).该锁存器基于单点翻转自恢复的双联互锁存储单元(dual interlocked storage cell,DICE),构建三模冗余容错机制,输出端级联“三中取二”表决器,可以有效地容忍单粒子多点翻转,表决输出正确逻辑值,不会出现高阻态,可以有效地屏蔽电路内部节点的软错误.该锁存器能够100%容忍三点翻转,四点翻转的容忍率高达90.30%.通过运用高速传输路径、时钟选通技术和钟控表决器,该锁存器有效地降低了功耗.32 nm工艺下SPICE仿真表明,与加固性能最好的三点翻转加固锁存器综合比较,LPMNUHL的延迟平均降低了40.16%,功耗平均降低了44.96%,功耗延迟积平均降低了65.40%,面积平均降低了34.60%,并且对电压/温度波动不敏感.

Design of Multiple Node Upset Tolerant Latch in 32 nm CMOS Technology

With continuous scaling of CMOS technology,single event multi-node upset induced by charge sharing effect has become an important factor affecting chip reliability.This paper proposed a novel multi-node upset(MNU)tolerant latch design:LPMNUHL.Based on DICE latch,where single node upset is resilient,the latch builds a mechanism of triple modular redundancy and uses a voter as output.The proposed latch is tolerant to multi-node upset and votes the correct output logic value.What’s more,there is no high impedance state in the latch and soft errors of the internal nodes can be blocked successfully.The latch can not only tolerance triple node upset completely,but also tolerance 90.30%of quadruple node upset.Due to the use of a high-speed transmission path,the clock-gating technology and a clock-gating voter,the proposed latch is low power.In 32 nm CMOS technology,extensive SPICE simulation results demonstrate that compared with the previous latches,the proposed latch has an average delay reduction of 40.16%,an average power reduction of 44.96%,an average power delay product reduction of 65.40%,and an area reduction of 34.60%.Moreover,the proposed latch is not sensitive to temperature and voltage variations.