有限状态熵编码的VLSI设计与实现

在处理海量数据时,以软件方式实现的Z标准(Zstd)无损压缩算法难以满足特定应用领域对压缩速度的需求.对Zstd进行硬件加速设计是解决这一问题的有效方案,尤其是针对Zstd的有限状态熵编码(finitestateentropy,FSE)的硬件加速.因此,提出一种适用于Zstd的FSE压缩、解压硬件实现架构,采用固定压缩表实现最优的硬件加速步骤;通过增加序列映射的硬件模块来降低存储空间并提高传输速度;采用软硬件协同设计方案,并对硬件实现架构进行7级流水设计.通过VisualStudio与Modelsim的联合验证平台进行验证,实验结果表明在TSMC55 nm的工艺下,系统最高频率可达到750 MHz.与软件实现相比,整体压缩速度提高了9倍以上,整体解压速度提高了约100倍.

Design and Implementation of VLSI for Finite State Entropy Encoding

The Zstd(Zstandard)lossless compression algorithm that implemented by software is difficult to meet the demand of compression speed in specific application field when processing massive data.It is an effective solution to this problem by using the hardware acceleration scheme,especially for the hardware acceleration of FSE(finite state entropy).Thus,a hardware implementation of the compression and decompression in FSE is proposed for Zstd.This scheme determines the optimal hardware acceleration step by fixing the size of compression table,reduces the storage space and improves the transmission speed by adding hardware modules of sequence mapping,enhances the time of parallel processing by dividing the seven-stages of flow and realizes the architecture by software and hardware collaboration.The proposed architecture is implemented in the TSMC 55 nm process,and the highest frequency can reach 750 MHz.The experimental results show that compared with the software implementation,the speed of the whole compression is more than 9 times faster,the speed of the whole decompression is more than the 100 times faster.