90nm和65nm工艺下片上网络互连串扰故障模型分析

随着晶体管制造尺寸的越来越小,集成密度的越来越高,耦合电容与电感之间所引起的相邻互连线间的干扰噪声成倍增加,对高速高密度纳米级超大规模集成电路造成极大危害。阐述了包括片上网络（Network-on-Chip,NoC）在内的高速互连电路串扰型故障的基本原理及串扰耦合模型,阐述了高速互连电路串扰型故障测试的主次因素机理等,并用HSPICE仿真验证了基于90nm和65nm的NoC参数下MA、MT故障模型中U型传输线线宽和线间距对串扰的影响。仿真结果表明,线间距越小,线间的高速互连串扰现象愈明显。

Analysis of interconnection crosstalk fault model of Network-on-Chip under technique of 90 nm and 65 nm

As the size of the transistor is made of smaller,more and more high density of integration,the interference noise of the coupled capacitances and inductances between the adjacent to the interconnection lines increase rapidly,and result in great harmful in higher speed and density of nanotechnology of VLSI.The basic test principles of crosstalk fault of high-speed interconnect circuit and crosstalk coupled model,such as in Network-on-Chip（NoC）,are indicated in this paper.The relevant mechanism of crosstalk fault model test between the high speed interconnection lines are also described.The simulation verified the crosstalk effect of the line wide and space between lines of the U-transmission line model of MA and MT fault model with HSPICE based on the NoC parameters of 90nm and 65nm.The simulation results indicate that the less of the space between lines are,the more obvious of the interconnection crosstalk of high speed become.