| 3D-SIC中多链式可配置容错结构术 |
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| 引用本文： | 王伟,董福弟,方芳,兰方勇,陈田,刘军.3D-SIC中多链式可配置容错结构术[J].电子测量与仪器学报,2012,26(2):126-131. |
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| 作者姓名： | 王伟 董福弟 方芳 兰方勇 陈田 刘军 |
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| 作者单位： | 1. 合肥工业大学系统结构实验室,合肥230009;合肥工业大学情感计算与先进智能机器安徽省重点实验室,合肥230009
2. 合肥工业大学管理学院,合肥,230009 |
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| 基金项目： | 国家自然科学基金项目（No.61106037）;博士点基金新教师项目（No.200803591033）;合肥工业大学研究生教改项目（YJG2010X10） |
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| 摘 要： | 三维（3-Dimension）芯片结构由于有着高密度、高速率、低功耗等优点而逐渐成为超大规模集成电路技术中的热门研究方向之一，在3D结构中通过使用硅通孔来连接垂直方向上的不同模块单元。但TSV在生产过程中会出现部分失效，导致整个芯片的失效。鉴于此，提出了多链式可配置容错结构，通过配置交叉开关单元，将TSV链与增加的冗余TSV导通的方法实现失效TSV的修复。实验表明整体修复率可以达到99％以上，同时面积开销和传输延迟也较低。
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| 关 键 词： | 三维 过硅通孔 修复 容错 |
Multi-chain type configurable fault-tolerant scheme in 3D-SIC |
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| Wang Wei
,
Dong Fudi
,
Fang Fang
,
Lan Fangyong
,
Chen Tian
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Liu Jun.Multi-chain type configurable fault-tolerant scheme in 3D-SIC[J].Journal of Electronic Measurement and Instrument,2012,26(2):126-131. |
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| Authors: | Wang Wei Dong Fudi Fang Fang Lan Fangyong Chen Tian Liu Jun |
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| Affiliation: | 1. Studio of Computer Architecture, Hefei University of Technology, Hefei 230009, China; 2. School of Management, Hefei University of Technology, Hefei 230009, China; 3. AnHui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, Hefei University of Technology, Hefei 230009, China) |
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| Abstract: | Owing to high density, high frequency and low power,3-Dimension（3D） chip structure is becoming one of the most popular academic research field in Very Large Scale Integrated Circuits（VLSI）. Vertical Through-Silicon-Vias （TSV） structure is used to connect vertical modules units. But in the production process, parts of them will be fail, this will lead to the whole chip can not work normally. Therefore, a configurable fault-tolerant structure with multiple TSV chain is presented. By configuring the switch unit, the TSV chain with failure TSV would be connected to the redundant TSV then resume the chip. The experiment results show that the overall chip recovery rate can reach to more than 99%, meanwhile the area overhead and the signal delay are both lower. |
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| Keywords: | 3D Through-Silicon-Vias recovery fault-tolerant |
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