一种节约面积的可编程存储器内建自测试设计方法

随着深亚微米技术不断的发展,在SoC设计中存储器需求越来越大,芯片的量产需要有效率而又具有相对的低成本的测试方法.可编程存储器内建自测试方法基于客制化的控制器,提供了一定程度可靠的弹性以及所需合理的硬件成本.我们在本文提出了一个P-MBIST设计的硬件分享架构,经由分享共用的地址产生器与控制器,P-MBIST电路的面积开销能够大幅减小,利用加入的两级流水线能够达到更高的测试速度.最后,所提出的P-MBIST电路能够由使用者自定义的配置文档而自动生成.

An Area-Efficient Design for Programmable Memory Built-In Self Test

As the progress of deep submicron technology,embedded memory grows greatly in the System-on-Chip design.An efficient test method with relatively low cost is required for mass production process.Programmable Built-In Self-Test（P-MBIST） solution provides a certain degree of flexibility with reasonable hardware cost,based on the customized controller/processor.In this work,we propose a hardware sharing architecture for P-MBIST design.Through sharing the common address generator and controller,the area overhead of P-MBIST circuit can be significantly reduced.Higher testing speed can be achieved by inserting two pipeline stages.Finally,the proposed P-MBIST circuit can be automatically generated from the user-defined configuration file.