| AHB-Wishbone总线桥的设计与实现 |
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| 引用本文： | 万静,王宏滨.AHB-Wishbone总线桥的设计与实现[J].自动化技术与应用,2010,29(2):54-57. |
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| 作者姓名： | 万静 王宏滨 |
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| 作者单位： | 哈尔滨理工大学,计算机科学与技术学院,黑龙江,哈尔滨,150080 |
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| 摘 要： | 为了实现SOC中集成在不同总线上的IP之间进行有效的通信,通过比较AHB总线和Wishbone总线的协议,本文提出了一种基于有限状态机的AHB-Wishbone总线桥的设计,并使用System Verilog语言实现。设计结果通过在ModelSim工具下的功能仿真,表明该总线桥符合片上总线转换的要求。
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| 关 键 词： | AHB总线 Wishbone总线 总线桥 |
Design and Reseach of AHB-Wishbone Bus Bridge |
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| WAN Jing,WANG Hong-bin.Design and Reseach of AHB-Wishbone Bus Bridge[J].Techniques of Automation and Applications,2010,29(2):54-57. |
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| Authors: | WAN Jing WANG Hong-bin |
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| Affiliation: | (School of Computer Science and Technology,Harbin University of Science and Technology,Harbin 150080 China) |
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| Abstract: | In order to achieve communication between different IPs which integrated on different buses of the SOC,through compare AHB bus protocol with Wishbone bus protocol,the paper introduces a design model of AHB-Wishbone bus bridge based on finish state machine,by using System Verilog language.The implementation of passed function simu-lation by ModelSim indicates that the bus bridge meets the requirement of On-Chip bus conversion. |
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| Keywords: | AHB bus Wishbone bus bus bridge |
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