Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

Computer simulations with the Spectre circuit simulator from Cadence Design Systems and a proton-accelerator experiment are conducted to investigate the relationship of single-event-upset (SEU) susceptibility to memory-cell layout in the context of a 0.18-μm CMOS SRAM using the dual interlocked storage cell (DICE) technology with differing separations of the pair transistors designed to store a 0 or 1, namely, 0.9 and 2.5 μm, respectively. The simulated values of critical charge for an upset are found to be greater by a factor of 10 for the wider separation. With 1-GeV proton irradiation, using the wider separation of pair transistors is found to reduce the SEU count by a factor of 5.5–15 (depending on the supply voltage). In the experiment, lowering the supply voltage of the memory bank from 1.8 to 0.7 V is found to increase on average the SEU cross section by a factor of 3. Close agreement is observed between the simulated and measured results.