X光安检机控制信号时钟提取的设计与实现

针对X光安检机系统控制信号传输中采用传统串行通信方式所存在的问题,提出一种利用数字锁相环技术实现串行数据时钟提取的硬件解决方案。该设计基于FPGA进行开发,并针对安检机中串行控制数据传输的数字锁相环进行研究,设计了适用于FPGA的串行时钟提取系统,最终采用Verilog语言实现。该设计经过安检机系统的硬件平台实际测试,最终经过Signal TapⅡ读取实时数据进行验证,可以论证该方案的时钟捕捉周期短,捕捉精度也满足安检机系统要求,从而实现了安检机系统数字控制信号的单线路传输,有效地提高传输的可靠性。

Design and Implementation of the Control Signal Clock Recovery Based on X-Ray Security Inspection Equipment

A hardware solution of achieving serial data clock recovery by using phase locked loop is proposed,aiming at the existed problems of adopting traditional serial communication in the control signal transmission of X-ray security inspection system.The design is developed based on FPGA,the digital phase locked loop of serial control data transmission in the secu-rity inspection equipment(SIE) is researched,a serial clock recovery system for FPGA is designed,and the designs is realized by Verilog.The design is ...