首页 | 本学科首页   官方微博 | 高级检索  
     

指令集仿真器的关键技术
引用本文:付琳,胡锦,梁利平.指令集仿真器的关键技术[J].计算机应用,2015,35(5):1421-1425.
作者姓名:付琳  胡锦  梁利平
作者单位:1. 湖南大学 物理与微电子科学学院, 长沙 410082; 2. 中国科学院 微电子研究所, 北京 100029
摘    要:为适应嵌入式系统开发中对指令集仿真器仿真速度的要求,提出一种改进的指令集仿真技术.该技术在现有的静态多核仿真器基础上引入指令预处理、动态译码缓存、多线程C函数生成和动态调度运行等技术,以实现对仿真器性能的优化.该技术已成功应用于中国科学院微电子所自主研发的IME-Diamond DSP处理器的多核指令集仿真器OPT-ISS中.实际应用程序测试结果表明,该技术在仿真速度提升方面有明显效果.

关 键 词:多核  指令集仿真器  多线程  译码缓存  C函数生成  
收稿时间:2014-12-17
修稿时间:2015-02-24

Key techniques for fast instruction set simulator
FU Lin,HU Jin,LIANG Liping.Key techniques for fast instruction set simulator[J].journal of Computer Applications,2015,35(5):1421-1425.
Authors:FU Lin  HU Jin  LIANG Liping
Affiliation:1. College of Physics and Microelectronics, Hunan University, Changsha Hunan 410082, China;
2. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Abstract:In order to adapt to the the requirement of the Instruction Set Simulator (ISS) simulation speed in embedded system development, an improved ISS technology was put forward.The technology introduced instruction preprocessing, dynamic decode cache structure, multi-thread C function generation and dynamic scheduling technique based on the existing static multi-core simulator to achieve the optimization of the simulator performance. This technique has been applied successfully in forming OPT-ISS, which is based on IME-Diamond multi-core DSP processor. The experimental results show that this technique improves the simulation speed indeed.
Keywords:multi-core  Instruction Set Simulator (ISS)  multi-thread  decoding cache  C function generation
本文献已被 万方数据 等数据库收录!
点击此处可从《计算机应用》浏览原始摘要信息
点击此处可从《计算机应用》下载全文
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号