On Random Pattern Testability of Cryptographic VLSI Cores

In this paper we show, that the statistical properties of cryptographic algorithms are the reason for the excellent pseudorandom testability of cryptographic processor cores. The work is especially concerned with modern symmetric block encryption algorithms and their VLSI implementations. For the examination typical basic operations of these cryptographic algorithms are categorized in classes and analyzed regarding their pseudorandom properties. Based on the results the pseudorandom properties of symmetric block ciphers can be determined by means of data flow graphs (DFG) and so-called predecessor operation lists. This is demonstrated with a paradigm algorithm, the symmetric block cipher 3WAY. The results of the theoretical analysis lead to a so-called global BIST concept for cryptographic processor cores. This self-test approach is characterized by central pseudorandom pattern generators and signature registers at the primary inputs and outputs of the cores. The global BIST is exemplarily applied to an implementation of the 3WAY algorithm. Finally, the quality of the developed test approach is determined by fault simulations.