高速缓冲存储器的设计与实现

随着芯片集成度的提高，在高速CPU与低速内存之间插入有缓冲作用的速度较快、容量较小的高速缓冲存储器，解决了两者速度的平衡和匹配问题，对微处理器整体性能有很大提高。本文从高速缓存的结构和基本理论出发，理论结合实际，介绍了32位高性能、低功耗嵌入式微处理器中高速缓存的实现方法，从RTL设计到版图设计的各个部分进行了论述，并介绍了该模块全定制部分电路和版图的实现。

Design and Implementation of Cache Memory

The cache between high speed CPU and low speed system memory can provide a primary pool of reusable instructions and data that can access more frequently by the processor, this method will solve the speed matching between CPU and system memory and has a direct effect on the microprocessor performance. This paper introduces the cache design of 32 b embedded CPU with high performance and low power consumption, and describes the implementation of full-custom circuit and layout in this module.