Analysis and Implementation of an Interleaved ZVS Converter with High Input Voltage

An interleaved half‐bridge converter is presented for high input voltage application. The features of the proposed converter are zero voltage switching (ZVS) turn‐on for all active switches, ripple current reduction at output side, load current sharing and load voltage regulation. Two half‐bridge converters connected in series and two split capacitors are used to limit the voltage stress of each power switch at one‐half of input DC bus voltage. Thus, active switches with low voltage stress can be used at high input voltage application. On the other hand, the output sides of two half‐bridge converters are connected in parallel to share the load current and reduce the current stresses of the secondary windings and the rectifier diodes. Since two half‐bridge converters are operated with interleaved pulse‐width modulation (PWM), the output ripple current can partially cancel each other such that the resultant ripple current at output side is reduced and the size of output inductors can be reduced. In each half‐bridge converter, asymmetrical PWM scheme is used to regulate the output voltage. Based on the resonant behavior by the output capacitance of MOSFETs and the leakage inductance (or external inductance) of transformers, active switches can be turned on at ZVS during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The proposed converter can be applied for high input voltage applications such as three‐phase 380‐V utility system. Finally, experiments based on a laboratory prototype with 960‐W rated power are provided to demonstrate the performance of proposed converter. Copyright © 2012 John Wiley & Sons, Ltd.