A Survey on Lifting-based Discrete Wavelet Transform Architectures

In this paper, we review recent developments in VLSI architectures and algorithms for efficient implementation of lifting based Discrete Wavelet Transform (DWT). The basic principle behind the lifting based scheme is to decompose the finite impulse response (FIR) filters in wavelet transform into a finite sequence of simple filtering steps. Lifting based DWT implementations have many advantages, and have recently been proposed for the JPEG2000 standard for image compression. Consequently, this has become an area of active research and several architectures have been proposed in recent years. In this paper, we provide a survey of these architectures for both 1-dimensional and 2-dimensional DWT. The architectures are representative of many design styles and range from highly parallel architectures to DSP-based architectures to folded architectures. We provide a systematic derivation of these architectures along with an analysis of their hardware and timing complexities. Tinku Acharya received his B.Sc. (Honors) in Physics, B.Tech. and M.Tech. in Computer Science from University of Calcutta, India, and the Ph.D. in Computer Science from University of Central Florida, USA, in 1984, 1987, 1989, and 1994, respectively. He is currently the Chief Technology Officer of Avisere Inc., Tucson, Arizona, USA. Dr. Acharya is also an Adjunct Professor in the Department of Electrical Engineering, Arizona State University, Tempe, USA. Before joining Avisere, Dr. Acharya served in Intel Corporation (1996–2002), where he led several R&D teams toward development of algorithms and architectures in image and video processing, multimedia computing, PC-based digital camera, reprographics architecture for color photo-copiers, 3G cellular telephony, analysis of next-generation microprocessor architecture, etc. Before Intel, Dr. Acharya was a consulting engineer at AT&T Bell Laboratories (1995–1996), a research faculty at the Institute of Systems Research, Institute of Advanced Computer Studies, University of Maryland at College Park (1994–1995), and held visiting faculty positions at Indian Institute of Technology, Kharagpur. He served as Systems Analyst in National Informatics Center, Planning Commission, Government of India (1988–1990). He collaborated in research and development with Xerox Palo Alto Research Center (PARC), Eastman Kodak Corporation, and many other institutions worldwide. Dr. Acharya is inventor of 88 US patents and 14 European patents. He authored over 80 technical papers and four books—Image Processing: Principles and Applications (Wiley, New Jersey, 2005), JPEG2000 Standard for Image Compression: Concepts, Algorithms, and VLSI Architectures (Wiley, 2004), Information Technology: Principles and Applications (Prentice-Hall India, 2004), and Data Mining: Multimedia, Soft Computing and Bioinformatics (Wiley, 2003). Dr. Acharya is a Fellow of the National Academy of Engineers (India), Life Fellow of the Institution of Electronics and Telecommunication Engineers (FIETE), and Senior Member of IEEE. His current research interests are in computer vision, image processing, multimedia data mining, bioinformatics, and VLSI architectures and algorithms. Chaitali Chakrabarti received the B.Tech. degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India in 1984, and the M.S. and Ph.D degrees in electrical engineering from the University of Maryland at College Park, USA, in 1986 and 1990 respectively. Since August 1990, she has been with the Department of Electrical Engineering, Arizona State University, Tempe, where she is now a Professor. Her research interests are in the areas of low power embedded systems design including memory optimization, high level synthesis and compilation, and VLSI architectures and algorithms for signal processing, image processing and communications. Dr. Chakrabarti is a member of the Center for Low Power Electronics, the Consortium for Embedded Systems and Connection One. She received the Research Initiation Award from the National Science Foundation in 1993, a Best Teacher Award from the College of Engineering and Applied Sciences, ASU, in 1994, and the Outstanding Educator Award from the IEEE Phoenix section in 2001. She has served on the program committees of ICASSP, ISCAS, SIPS, ISLPED and DAC. She is currently an Associate Editor of the IEEE Transactions on Signal Processing and the Journal of VLSI Signal Processing Systems. She is also the TC Chair of the sub-committee on Design and Implementation of Signal Processing Systems, IEEE Signal Processing Society.