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Analog Circuit Fault Detection Using Location of Poles
Authors:Ashok Kavithamani  Venugopal Manikandan  Nanjundappan Devarajan
Affiliation:(1) Department of Electrical and Electronics Engineering, Coimbatore Institute of Technology, Coimbatore, 641 014, India;(2) Department of Electrical and Electronics Engineering, Government College of Technology, Coimbatore, 641 013, India
Abstract:A method for detection of parametric faults occurring in linear analog circuits based on location of poles of the Circuit Under Test (CUT) is proposed. In the proposed method, the value of each component of the CUT is varied within its tolerance limit using monte carlo simulation. The upper and lower bounds of magnitude, phase angle, real part and imaginary part of all poles of the CUT are obtained. While testing, the locations of poles are obtained. If any one or more of the poles lies outside the tolerance limit then the CUT is declared faulty. The effectiveness of the proposed method is validated through two benchmark circuits like second order sallenkey band pass filter and fourth order leapfrog low pass filter.
Keywords:
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