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| TD-LTE终端性能优化 | |
| 引用本文： | 刘飞,商群峰,黄林鹏,饶卫雄. TD-LTE终端性能优化[J]. 计算机工程, 2011, 37(19): 255-257. DOI: 10.3969/j.issn.1000-3428.2011.19.084 |
| 作者姓名： | 刘飞 商群峰 黄林鹏 饶卫雄 |
| 作者单位： | 1. 上海贝尔股份有限公司,上海,201206 2. 上海交通大学计算机科学与工程系,上海,200240 3. 香港科技大学计算机科学与工程系,香港,999077 |
| 摘 要： | 给出TD-LTE终端的优化方法，使其能连续、稳定、实时地测试演进型Node B(eNodeB)。该终端由1个现场可编程门阵列和2个数字信号处理器构成，能够实现手机物理层的上下行链路。在测试TD-LTE终端时，可以模拟手机发送上行数据给NodeB并处理eNodeB发送的下行数据。采用搬移内存、硬件加速和分布式多核计算的机制，实现物理下行共享信道和上行共享信道(PUSCH)的优化。 |
| 关 键 词： | 上行链路 下行链路 数字信号处理器 多核 终端 |
| 收稿时间： | 2011-03-21 |
TD-LTE Terminal Performance Optimization |
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| LIU Fei,SHANG Qun-feng,HUANG Lin-peng,RAO Wei-xiong. TD-LTE Terminal Performance Optimization[J]. Computer Engineering, 2011, 37(19): 255-257. DOI: 10.3969/j.issn.1000-3428.2011.19.084 | |
| Authors: | LIU Fei SHANG Qun-feng HUANG Lin-peng RAO Wei-xiong |
| Affiliation: | 1.Shanghai Bell Co.Ltd.,Shanghai 201206,China;2.Department of Computer Science and Engineering,Shanghai Jiaotong University,Shanghai 200240,China;3.Department of Computer Science and Engineering,Hong Kong University of Science and Technology,Hong Kong 999077,China) |
| Abstract: | This paper gives a proposal to optimize terminal（User Equipment（UE）） to be consecutive,stable and real time.The UE consists of one Field Programmable Gate Array（FPGA） and two Digital Signal Processors（DSP）.UE physical channel are implemented,which can be used in TD-LTE test.UE can send the UL data to evolved Node B（eNodeB） and process the DL data from eNodeB.This paper focuses on the optimization of Physical Downlink Share Channel（PDSCH） and Physical Uplink Share Channel（PUSCH）.Memory move,hardware accelerate and distribute multi core computing are adopted.In the above way,this UE can process PDSCH and PUSCH in 1 ms.As expected,UE can run consecutively,stably and real time. |
| Keywords: | uplink downlink Digital Signal Processor（DSP） multicore terminal |
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