A 10-bit low power SAR A/D converter based on 90 nm CMOS |
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| Tong Xingyuan, Yang Yintang, Zhu Zhangming, Xiao Yan, Chen Jianming. A 10-bit low power SAR A/D converter based on 90 nm CMOS[J]. Journal of Semiconductors, 2009, 30(10): 105008. doi: 10.1088/1674-4926/30/10/105008 Tong X Y, Yang Y T, Zhu Z M, Xiao Y, Chen J M. A 10-bit low power SAR A/D converter based on 90 nm CMOS[J]. J. Semicond., 2009, 30(10): 105008. doi: 10.1088/1674-4926/30/10/105008.Export: BibTex EndNote |
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| Authors: | Tong Xingyuan Yang Yintang Zhu Zhangming Xiao Yan Chen Jianming |
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| Affiliation: | Institute of Microelectronics, Xidian University, Xi’an 710071, China;Institute of Microelectronics, Xidian University, Xi’an 710071, China;Institute of Microelectronics, Xidian University, Xi’an 710071, China;IP-2 of D. S. Division, Semiconductor Manufacturing International Corporation, Shanghai 201203, China;IP-2 of D. S. Division, Semiconductor Manufacturing International Corporation, Shanghai 201203, China |
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| Abstract: | Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW. |
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| Keywords: | analog-to-digital converter R-C combination CMOS integrated circuits nonlinearity low power |
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